OBSAH WEBU
ČTĚTE!
Rozdíly
Zde můžete vidět rozdíly mezi vybranou verzí a aktuální verzí dané stránky.
|
temata:10-principy_vhdl:main [2011/03/31 13:54] vagabund |
temata:10-principy_vhdl:main [2011/03/31 14:12] (aktuální) vagabund |
||
|---|---|---|---|
| Řádek 1: | Řádek 1: | ||
| + | ~~ODT~~ | ||
| + | |||
| ====== 10 - Principy VHDL ====== | ====== 10 - Principy VHDL ====== | ||
| Řádek 519: | Řádek 521: | ||
| </code> | </code> | ||
| + | === Výběrové přiřazení signálu === | ||
| + | <code vhdl> | ||
| + | with expression select | ||
| + | signal_name <=expression when value{, expression when value}; | ||
| + | </code> | ||
| + | |||
| + | <code vhdl> | ||
| + | with MYSEL select | ||
| + | Z <= A when 15, | ||
| + | B when 22, | ||
| + | C when 28; | ||
| + | </code> | ||
| + | |||
| + | === Podmíněné přiřazení signálu === | ||
| + | <code vhdl> | ||
| + | signal_name <=expression when condition else | ||
| + | {expression when condition else} | ||
| + | </code> | ||
| + | |||
| + | **Příklad:** | ||
| + | <code vhdl> | ||
| + | Z <= A when (X > 3) else | ||
| + | B when (X < 3) else | ||
| + | C; | ||
| + | </code> | ||
| + | |||
| + | ==== Příklady ==== | ||
| + | |||
| + | === Multiplexor === | ||
| + | |||
| + | <code vhdl> | ||
| + | library ieee; | ||
| + | use ieee.std_logic_1164.all; | ||
| + | entity Mux is | ||
| + | port( I3: in std_logic_vector(2 downto 0); | ||
| + | I2: in std_logic_vector(2 downto 0); | ||
| + | I1: in std_logic_vector(2 downto 0); | ||
| + | I0: in std_logic_vector(2 downto 0); | ||
| + | S: in std_logic_vector(1 downto 0); | ||
| + | O: out std_logic_vector(2 downto 0) | ||
| + | ); | ||
| + | end Mux; | ||
| + | |||
| + | -- varianta 1 | ||
| + | architecture behv1 of Mux is | ||
| + | begin | ||
| + | process(I3,I2,I1,I0,S) | ||
| + | begin | ||
| + | -- příkaz case | ||
| + | case S is | ||
| + | when "00" => O <= I0; | ||
| + | when "01" => O <= I1; | ||
| + | when "10" => O <= I2; | ||
| + | when "11" => O <= I3; | ||
| + | when others => O <= "XXX"; | ||
| + | end case; | ||
| + | end process; | ||
| + | end behv1; | ||
| + | |||
| + | -- varianta 2 | ||
| + | architecture behv2 of Mux is | ||
| + | begin | ||
| + | -- příkaz when.. else | ||
| + | O <= I0 when S="00" else | ||
| + | I1 when S="01" else | ||
| + | I2 when S="10" else | ||
| + | I3 when S="11" else | ||
| + | "XXX"; | ||
| + | end behv2; | ||
| + | </code> | ||
| + | |||
| + | === Dekodér === | ||
| + | |||
| + | <code vhdl> | ||
| + | library IEEE; | ||
| + | use IEEE.std_logic_1164.all; | ||
| + | entity dec3to8 is | ||
| + | port ( | ||
| + | addr: in STD_LOGIC_VECTOR (2 downto 0); | ||
| + | y: out STD_LOGIC_VECTOR (7 downto 0) | ||
| + | ); | ||
| + | end dec3to8; | ||
| + | |||
| + | architecture dec3to8 of dec3to8 is | ||
| + | begin | ||
| + | with addr select | ||
| + | y <= "10000000" when "111", | ||
| + | "01000000" when "110", | ||
| + | "00100000" when "101", | ||
| + | "00010000" when "100", | ||
| + | "00001000" when "011", | ||
| + | "00000100" when "010", | ||
| + | "00000010" when "001", | ||
| + | "00000001" when others; | ||
| + | end dec3to8; | ||
| + | </code> | ||
| + | |||
| + | alternativně pomocí procesu: | ||
| + | |||
| + | <code vhdl> | ||
| + | process(addr) | ||
| + | begin | ||
| + | y <= "00000000"; | ||
| + | case addr is | ||
| + | when "000" => y <= "00000001"; | ||
| + | when "001" => y <= "00000010"; | ||
| + | when "010" => y <= "00000100"; | ||
| + | when "011" => y <= "00001000"; | ||
| + | when "100" => y <= "00010000"; | ||
| + | when "101" => y <= "00100000"; | ||
| + | when "110" => y <= "01000000"; | ||
| + | when "111" => y <= "10000000"; | ||
| + | when others => null; | ||
| + | end case; | ||
| + | end process; | ||
| + | </code> | ||
| + | |||
| + | === ALU === | ||
| + | |||
| + | <code vhdl> | ||
| + | library ieee; | ||
| + | use ieee.std_logic_1164.all; | ||
| + | use ieee.std_logic_unsigned.all; | ||
| + | use ieee.std_logic_arith.all; | ||
| + | |||
| + | entity ALU is | ||
| + | port( A: in std_logic_vector(1 downto 0); | ||
| + | B: in std_logic_vector(1 downto 0); | ||
| + | Sel: in std_logic_vector(1 downto 0); | ||
| + | Res: out std_logic_vector(1 downto 0) | ||
| + | ); | ||
| + | end ALU; | ||
| + | |||
| + | architecture behv of ALU is | ||
| + | begin | ||
| + | process(A,B,Sel) | ||
| + | begin | ||
| + | case Sel is | ||
| + | when "00" => Res <= A + B; | ||
| + | when "01" => Res <= A + (not B) + 1; | ||
| + | when "10" => Res <= A and B; | ||
| + | when "11" => Res <= A or B; | ||
| + | when others => Res <= "XX"; | ||
| + | end case; | ||
| + | end process; | ||
| + | end behv; | ||
| + | </code> | ||
| + | |||
| + | <note> | ||
| + | Další popisu obvodů lze nalézt [[https://www.fit.vutbr.cz/study/courses/INP/private/cvic/inp_vhdl_opora.pdf|zde]] od strany 25. | ||
| + | </note> | ||
| + | |||
| + | ===== Potvrzení ===== | ||
| + | |||
| + | <doodle single login|10> | ||
| + | ^ OK ^ !!! ^ | ||
| + | </doodle> | ||
| + | |||
| + | {{tag>vagabund INP vhdl}} | ||
| + | |||
| + | ~~DISCUSSION~~ | ||
